This invention relates generally to non-volatile semiconductor memories such as electrically erasable programmable read-only memory (EEPROM) and flash EEPROM, and specifically ones with improved partial page program capability.
Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as a small form factor card, has recently become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products. Flash memory, both, embedded and in the form of a removable card is ideally suited in the mobile and handheld environment because of its small size, low power consumption, high speed and high reliability features.
EEPROM utilizes a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) that must be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions.
The floating gate can hold a range of charges and therefore can be programmed to any threshold voltage level within a threshold voltage window. The size of the threshold voltage window is delimited by the minimum and maximum threshold levels of the device, which in turn correspond to the range of the charges that can be programmed onto the floating gate. The threshold window generally depends on the memory device's characteristics, operating conditions and history. Each distinct, resolvable threshold voltage level range within the window may, in principle, be used to designate a definite memory state of the cell.
The transistor serving as a memory cell is typically programmed to a “programmed” state by one of two mechanisms. In “hot electron injection,” a high voltage applied to the drain accelerates electrons across the substrate channel region. At the same time a high voltage applied to the control gate pulls the hot electrons through a thin gate dielectric onto the floating gate. In “tunneling injection,” a high voltage is applied to the control gate relative to the substrate. In this way, electrons are pulled from the substrate to the intervening floating gate.
The memory device may be erased by a number of mechanisms. For EEPROM, a memory cell is electrically erasable, by applying a high voltage to the substrate relative to the control gate so as to induce electrons in the floating gate to tunnel through a thin oxide to the substrate channel region (i.e., Fowler-Nordheim tunneling.) Typically, the EEPROM is erasable byte by byte. For flash EEPROM, the memory is electrically erasable either all at once or one or more blocks at a time, where a block may consist of 512 bytes or more of memory.
Examples of Non-Volatile Memory Cells
The memory devices typically comprise one or more memory chips that may be mounted on a card. Each memory chip comprises an array of memory cells supported by peripheral circuits such as decoders and erase, write and read circuits. The more sophisticated memory devices also come with a controller that performs intelligent and higher level memory operations and interfacing. There are many commercially successful non-volatile solid-state memory devices being used today. These memory devices may employ different types of memory cells, each type having one or more charge storage element.
FIGS. 1A-1E illustrate schematically different examples of non-volatile memory cells.
FIG. 1A illustrates schematically a non-volatile memory in the form of an EEPROM cell with a floating gate for storing charge. An electrically erasable and programmable read-only memory (EEPROM) has a similar structure to EPROM, but additionally provides a mechanism for loading and removing charge electrically from its floating gate upon application of proper voltages without the need for exposure to UV radiation. Examples of such cells and methods of manufacturing them are given in U.S. Pat. No. 5,595,924.
FIG. 1B illustrates schematically a flash EEPROM cell having both a select gate and a control or steering gate. The memory cell 10 has a “split-channel” 12 between source 14 and drain 16 diffusions. A cell is formed effectively with two transistors T1 and T2 in series. T1 serves as a memory transistor having a floating gate 20 and a control gate 30. The floating gate is capable of storing a selectable amount of charge. The amount of current that can flow through the T1's portion of the channel depends on the voltage on the control gate 30 and the amount of charge residing on the intervening floating gate 20. T2 serves as a select transistor having a select gate 40. When T2 is turned on by a voltage at the select gate 40, it allows the current in the T1's portion of the channel to pass between the source and drain. The select transistor provides a switch along the source-drain channel independent of the voltage at the control gate. One advantage is that it can be used to turn off those cells that are still conducting at zero control gate voltage due to their charge depletion (positive) at their floating gates. The other advantage is that it allows source side injection programming to be more easily implemented.
One simple embodiment of the split-channel memory cell is where the select gate and the control gate are connected to the same word line as indicated schematically by a dotted line shown in FIG. 1B. This is accomplished by having a charge storage element (floating gate) positioned over one portion of the channel and a control gate structure (which is part of a word line) positioned over the other channel portion as well as over the charge storage element. This effectively forms a cell with two transistors in series, one (the memory transistor) with a combination of the amount of charge on the charge storage element and the voltage on the word line controlling the amount of current that can flow through its portion of the channel, and the other (the select transistor) having the word line alone serving as its gate. Examples of such cells, their uses in memory systems and methods of manufacturing them are given in U.S. Pat. Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, and 5,661,053.
A more refined embodiment of the split-channel cell shown in FIG. 1B is when the select gate and the control gate are independent and not connected by the dotted line between them. One implementation has the control gates of one column in an array of cells connected to a control (or steering) line running perpendicular to the word line. The effect is to relieve the word line from having to perform two functions at the same time when reading or programming a selected cell. Those two functions are (1) to serve as a gate of a select transistor, thus requiring a proper voltage to turn the select transistor on and off, and (2) to drive the voltage of the charge storage element to a desired level through an electric field (capacitive) coupling between the word line and the charge storage element. It is often difficult to perform both of these functions in an optimum manner with a single voltage. With the separate control of the control gate and the select gate, the word line need only perform function (1), while the added control line performs function (2). This capability allows for design of higher performance programming where the programming voltage is geared to the targeted data. The use of independent control (or steering) gates in a flash EEPROM array is described, for example, in U.S. Pat. Nos. 5,313,421 and 6,222,762.
FIG. 1C illustrates schematically another flash EEPROM cell having dual floating gates and independent select and control gates. The memory cell 10 is similar to that of FIG. 1B except it effectively has three transistors in series. In this type of cell, two storage elements (i.e., that of T1—left and T1—right) are included over its channel between source and drain diffusions with a select transistor T1 in between them. The memory transistors have floating gates 20 and 20′, and control gates 30 and 30′, respectively. The select transistor T2 is controlled by a select gate 40. At any one time, only one of the pair of memory transistors is accessed for read or write. When the storage unit T1—left is being accessed, both the T2 and T1—right are turned on to allow the current in the T1—left's portion of the channel to pass between the source and the drain. Similarly, when the storage unit T1—right is being accessed, T2 and T1—left are turned on. Erase is effected by having a portion of the select gate polysilicon in close proximity to the floating gate and applying a substantial positive voltage (e.g. 20V) to the select gate so that the electrons stored within the floating gate can tunnel to the select gate polysilicon.
FIG. 1D illustrates schematically a string of memory cells organized into a NAND cell. A NAND cell 50 consists of a series of memory transistors M1, M2, . . . Mn (n=4, 8, 16 or higher) daisy-chained by their sources and drains. A pair of select transistors S1, S2 controls the memory transistors chain's connection to the external via the NAND cell's source terminal 54 and drain terminal 56. In a memory array, when the source select transistor S1 is turned on, the source terminal is coupled to a source line. Similarly, when the drain select transistor S2 is turned on, the drain terminal of the NAND cell is coupled to a bit line of the memory array. Each memory transistor in the chain has a charge storage element to store a given amount of charge so as to represent an intended memory state. A control gate of each memory transistor provides control over read and write operations. A control gate of each of the select transistors S1, S2 provides control access to the NAND cell via its source terminal 54 and drain terminal 56 respectively.
When an addressed memory transistor within a NAND cell is read and verified during programming, its control gate is supplied with an appropriate voltage. At the same time, the rest of the non-addressed memory transistors in the NAND cell 50 are fully turned on by application of sufficient voltage on their control gates. In this way, a conductive path is effectively created from the source of the individual memory transistor to the source terminal 54 of the NAND cell and likewise for the drain of the individual memory transistor to the drain terminal 56 of the cell. Memory devices with such NAND cell structures are described in U.S. Pat. Nos. 5,570,315, 5,903,495, 6,046,935.
FIG. 1E illustrates schematically a non-volatile memory with a dielectric layer for storing charge. Instead of the conductive floating gate elements described above, separate regions of the dielectric layer are used as the charge storage element. Such memory devices utilizing dielectric storage element have been described by Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, no. 11, November 2000, pp. 543-545. An ONO dielectric layer extends across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. For example, U.S. Pat. Nos. 5,768,192 and 6,011,725 disclose a nonvolatile memory cell having a trapping dielectric sandwiched between two silicon dioxide layers. Multi-state data storage is implemented by separately reading the binary states of the spatially separated charge storage regions within the dielectric.
Memory Array
A memory device typically contains a two-dimensional array of memory cells arranged in rows and columns and addressable by word lines and bit lines. The array can be formed according to an NOR type or a NAND type architecture.
Nor Array
FIG. 2 illustrates an example of an NOR array of memory cells. Memory devices with an NOR type architecture have been implemented with cells of the type illustrated in FIGS. 1B or 1C. Each row of memory cells are connected by their sources and drains in a daisy-chain manner. This design is sometimes referred to as a virtual ground design. Each memory cell 10 has a source 14, a drain 16, a control gate 30 and a select gate 40. The cells in a row have their select gates connected to word line 42. The cells in a column have their sources and drains respectively connected to selected bit lines 34 and 36. In some embodiments where the memory cells have their control gate and select gate controlled independently, a steering line 36 also connects the control gates of the cells in a column.
Many flash EEPROM devices are implemented with memory cells where each is formed with its control gate and select gate connected together. In this case, there is no need for steering lines and a word line simply connects all the control gates and select gates of cells along each row. Examples of these designs are disclosed in U.S. Pat. Nos. 5,172,338 and 5,418,752. In these designs, the word line essentially performs two functions: row selection and supplying control gate voltage to all cells in the row for reading or programming.
Nand Array
FIG. 3 illustrates an example of a NAND array of memory cells, such as that shown in FIG. 1D. Along each column of NAND cells, a bit line is coupled to the drain terminal 56 of each NAND cell. Along each row of NAND cells, a source line may connect all their source terminals 54. Also the control gates of the NAND cells along a row are connected to a series of corresponding word lines. An entire row of NAND cells can be addressed by turning on the pair of select transistors (see FIG. 1D) with appropriate voltages on their control gates via the connected word lines. When a memory transistor within the chain of a NAND cell is being read, the remaining memory transistors in the chain are turned on hard via their associated word lines so that the current flowing through the chain is essentially dependent upon the level of charge stored in the cell being read. An example of a NAND architecture array and its operation as part of a memory system is found in U.S. Pat. Nos. 5,570,315, 5,774,397 and 6,046,935.
Block Erase
Programming of charge storage memory devices can only result in adding more charge to its charge storage elements. Therefore, prior to a program operation, existing charge in a charge storage element must be removed (or erased). Erase circuits (not shown) are provided to erase one or more blocks of memory cells. A non-volatile memory such as EEPROM is referred to as a “Flash” EEPROM when an entire array of cells, or significant groups of cells of the array, is electrically erased together (i.e., in a flash). Once erased, the group of cells can then be reprogrammed. The group of cells erasable together may consist of one or more addressable erase units. The erase unit or block typically stores one or more pages of data, the page being the unit of programming and reading, although more than one page may be programmed or read in a single operation. Each page typically stores one or more sectors of data, the size of the sector being defined by the host system. An example is a sector of 512 bytes of user data, following a standard established with magnetic disk drives, plus some number of bytes of overhead information about the user data and/or the block in which it is stored.
Read/Write Circuits
In the usual two-state EEPROM cell, at least one breakpoint level is established so as to partition the conduction window into two regions. The state of the cell relative to the breakpoint is commonly determined using either “current” sense or “voltage” sense. Using current sense, a cell is read by applying predetermined, fixed voltages, its gate, source, and drain and the resulting current is compared to either an absolute value or to a value obtained from a similar cell whose threshold has been deliberately set to a mid value between the two extreme states. If the current read is higher than that of the breakpoint level, the cell is determined to be in one logical state (e.g., a “zero” state). On the other hand, if the current is less than that of the breakpoint level, the cell is determined to be in the other logical state (e.g., a “one” state). Thus, such a two-state cell stores one bit of digital information. A reference current source, which may be externally programmable, is often provided as part of a memory system to generate the breakpoint level current.
In order to increase memory capacity, flash EEPROM devices are being fabricated with higher and higher density as the state of the semiconductor technology advances. Another method for increasing storage capacity is to have each memory cell store more than two states.
For a multi-state or multi-level EEPROM memory cell, the conduction window is partitioned into more than two regions by more than one breakpoint such that each cell is capable of storing more than one bit of data. The information that a given EEPROM array can store is thus increased with the number of states that each cell can store. EEPROM or flash EEPROM with multi-state or multi-level memory cells have been described in U.S. Pat. No. 5,172,338.
In practice, the memory state of a cell is usually read by sensing the conduction current across the source and drain electrodes of the cell when a read level is applied to the control gate. Thus, for each given charge on the floating gate of a cell, a corresponding conduction current with respect to a fixed reference control gate voltage may be detected. Similarly, the range of charge programmable onto the floating gate defines a corresponding threshold voltage window or a corresponding conduction current window.
Alternatively, instead of detecting the conduction current among a partitioned current window (current sense), it is possible to set the threshold voltage for a given memory state under test at the control gate and detect if the conduction current is lower or higher than a threshold current (voltage sense). In one implementation the detection of the conduction current relative to a threshold current is accomplished by examining the rate the conduction current is discharging through the capacitance of the bit line; if the cell is programmed (a higher threshold relative to the gate voltage) the discharge current will be so small that the relatively large capacitance of the bit line will not be significantly discharged and the sense amplifier will return a “0” state.
U.S. Pat. No. 4,357,685 discloses a method of programming a 2-state EPROM in which when a cell is programmed to a given state, it is subject to successive programming voltage pulses, each time adding incremental charge to the floating gate. In between pulses, the cell is read back or verified to determine its source-drain current relative to the breakpoint level. Programming stops when the current state has been verified to reach the desired state. The programming pulse train used may have increasing period or amplitude.
Prior art programming circuits simply apply programming pulses to step through the threshold window from the erased or ground state until the target state is reached. Practically, to allow for adequate resolution, each partitioned or demarcated region would require at least about five programming steps to transverse. The performance is acceptable for 2-state memory cells. However, for multi-state cells, the number of steps required increases with the number of partitions and therefore, the programming precision or resolution must be increased. For example, a 16-state cell may require on average at least 40 programming pulses to program to a target state.
Memory array 100 is accessible by read/write circuits via a row decoder and a column decoder. As shown in FIGS. 2 and 3, a memory transistor of a memory cell in the memory array 100 is addressable via a set of selected word line(s) and bit line(s). The row decoder selects one or more word lines and the column decoder selects one or more bit lines in order to apply appropriate voltages to the respective gates of the addressed memory transistor. Read/write circuits are provided to read or write (program) the memory states of addressed memory transistors. The read/write circuits comprise a number of read/write modules connectable via bit lines to memory elements in the array.
During read or verify, a sense amplifier determines the current flowing through the drain of an addressed memory transistor connected via a selected bit line. The current depends on the charge stored in the memory transistor and its control gate voltage. For example, in a multi-state EEPROM cell, its floating gate can be charged to one of several different levels. For a 4-level cell, it may be used to store two bits of data. The level detected by the sense amplifier is converted by a level-to-bits conversion logic to a set of data bits to be stored in a data latch.
Factors Affecting Read/Write Performance and Accuracy
In order to improve read and program performance, multiple charge storage elements or memory transistors in an array are read or programmed in parallel. Thus, a logical “page” of memory elements are read or programmed together. In existing memory architectures, a row typically contains several interleaved pages. All memory elements of a page will be read or programmed together. The column decoder will selectively connect each one of the interleaved pages to a corresponding number of read/write modules. For example, in one implementation, the memory array is designed to have a page size of 532 bytes (512 bytes plus 20 bytes of overheads.) If each column contains a drain bit line and there are two interleaved pages per row, this amounts to 8512 columns with each page being associated with 4256 columns. There will be 4256 sense modules connectable to read or write in parallel either all the even bit lines or the odd bit lines. In this way, a page of 4256 bits (i.e., 532 bytes) of data in parallel are read from or programmed into the page of memory elements. The read/write modules forming the read/write circuits can be arranged into various architectures.
A highly compact and high performance non-volatile memory and method of control are described in U.S. patent application entitled “Highly Compact Non-Volatile Memory and Method Thereof,” Ser. No. 10/254,483, filed Sep. 24, 2002 by Raul-Adrian Cernea, which is incorporated herein by reference in its entirety.
FIGS. 4A and 4B illustrate the specific existing technique of programming a 4-state NAND memory cell in an array of the type described above. These two figures and the accompanying description of the programming process are taken from U.S. Pat. No. 6,522,580, which is incorporated herein by reference in its entirety.
FIGS. 4A and 4B show threshold voltage distributions for a 4-states NAND memory cell in an array of the type described above, where the floating gate of the cell in the array stores two bits of data, namely four data states, in each cell. The curve E represents a distribution of the threshold levels VT of the cell within the array that are in the erased state (“11” data state), being negative threshold voltage levels. In the event that the cells are set to states other than the above-described erased state as the initial state of the cells before programming of the cells, the curve E as used in this application also represents such states; more generally, all such states including the erased state are referred to herein as “reset states.” Threshold voltage distributions A and B of the storage elements storing “10” and “00” user data respectively, are shown to be between 0 volts and 1 volt and between 1 volt and 2 volts respectively. The curve C shows the distribution of memory cells that have been programmed to the “01” data states, being the highest threshold voltage levels more than 2 volts and less then 4.5 volts of the read past voltage. The terms “user data” and “host data” are used interchangeably herein.
Each of the two bits stored in a single memory cell is from a different logical page and may be programmed at different times. Each of the two bits carries a different logical page address from each other. The two bits stored in a single memory cell form an ordered set or pair of variables of binary values (a more significant bit and a less significant bit). The less significant bit in the user or host data “11”, “10”, “00” and “01” is accessed when the lower page address is input. The more significant bit of the user or host data is accessed when an upper page address is input. Where the data stored comprises more than two bits, the ordered set of stored values may include more than two variables. The logical page designation is different from the designation of even and odd or interleaved pages, which relate to the physical configuration of the memory cells in the memory array. The designating of logical pages can also be extended to where the threshold window is divided into finer divisions to allow for more than 4 states to be stored in the cells to represent more than two data bits per cell, so that more than two pages are used, in which case they may simply be referred to numerically, such as the first, second, third pages etc.
As noted above, prior to a program operation, one or more blocks of memory cells (also called charge storage elements herein) are electrically erased together, to the erased state “11.” Then the user or host data in the data buffer is then used to set the charge storage level or threshold level of the charge storage elements. In the first programming pass, the cell's threshold level is set according to the bits from the lower logical page in the data buffer. If that bit is a “1,” nothing is done since the cell is in an erased state as a result of having been earlier erased. However, if that bit is a “0,” the level of the cell is increased to the first programmed state A. That concludes the first programming pass.
In a second programming pass, the cell's threshold level is set according to the bit being stored in the data buffer from the upper logical page. If a “1,” no programming occurs since the cell is in one of the states E or A, depending upon the programming of the lower page bit, both of which carry an upper page bit of “1.” If the upper page bit is a “0,” however, the cell is programmed a second time. If the first pass resulted in the cell remaining in the erased state E, the cell is programmed from that state to the highest state C, as shown by the upper arrow in FIG. 4B. If the cell has been programmed into the state A, however, as a result of the first programming pass, the cell is further programmed in the second pass from that state to the state B, as shown by the lower arrow of FIG. 4B. The result of the second pass is to program the cell into the states designated to store a “0” from the upper page without changing the result of the first pass programming of the lower page bit.
During the second programming pass, where the upper page bit is a “0,” the cell should be programmed from either the erased state E to the highest state C or from the state A to the state B, in accordance with the upper and lower arrows in FIG. 4B. In order to determine whether the programming should occur in accordance with the upper or lower arrow, it is necessary to first determine whether the cell is in state E or A. In some devices, this is performed by a process known as internal read or internal data load, where a cell that has been programmed during a first programming pass is read to determine whether its threshold level corresponds to state E or A.
Field-effect coupling between adjacent floating gates of cells in the memory array of the type described above is described in U.S. Pat. No. 5,867,429 of Jian Chen and Yupin Fong, which patent is incorporated herein in its entirety by this reference. The degree of this coupling is necessarily increasing as the sizes of memory cell arrays are being decreased as the result of improvements of integrated circuit manufacturing techniques. The problem occurs most pronouncedly between two sets of adjacent cells that have been programmed at different times. One set of cells is programmed to add a level of charge to the floating gates that corresponds to one set of data. After the second set of cells is programmed with the second set of data, the charge levels read from the floating gates of the first set of cells often appear to be different than programmed because of the effect of the charges on the second set of floating gates being coupled with the first. This is known as the Yupin effect.
The above-described Yupin effect is particularly pronounced when the floating gates of the second set of cells programmed subsequently are programmed to a threshold level much higher than that of the floating gates of the first set of cells. From FIG. 4B, it is observed that when the floating gates of the second set of cells are programmed from the erased state E to the highest state C, the Yupin effect is the most pronounced because the change in threshold voltage is relatively large. One approach to reduce the Yupin effect is to program the states to their final value after the succeeding word line has been programmed. This is described in U.S. patent application Ser. No. 10/237,426 filed Sep. 6, 2002 by Raul-Adrian Cernea et al entitled “Techniques for Reducing Effects of Coupling Between Storage Elements of Adjacent Rows of Memory Cells,” which is incorporated herein in its entirety by reference. This application introduces the concept of “flag” cells within each page that indicate the programming state of that page (interim or final).
Another approach to reduce the Yupin effect is through the use of an alternative code scheme than the one set forth in FIGS. 4A and 4B as proposed in U.S. Pat. No. 6,657,891 by Shibata et al., which is incorporated herein in its entirety by reference. The code scheme proposed by Shibata et al. is shown in FIGS. 5A-5C. In FIGS. 5A-5C, it is envisioned that there may be more than two logical pages of data that can be represented by the threshold voltage levels of the memory cells, and for this reason, the lower logical page described above is referred to as the first page and upper logical page described above is referred to as the second page in FIGS. 5A-5C. As before, if the first page data to be written into memory cell is “1,” programming is not performed and the cell remains in the erased state E. If the first page data is a “0,” programming is carried out so that the threshold voltage of the memory cell is raised to one in a distribution or state B′ shown in FIG. 5A. This is in contrast to the process in FIG. 4A where a “0” value of the first page data would cause the cell to be programmed to state A. As shown in FIG. 5B, before second-page data is used for programming the cell, data is written to memory cells adjacent to the one already programmed into state B′. As a consequence of the Yupin effect due to the charges on the floating gates of the subsequently programmed adjacent cells, the threshold voltage distribution B′ has become wider or larger as shown in FIG. 5B compared to that in FIG. 5A. Note that even the initial distribution B′ of FIG. 5A is wider though always lower in value than the final distribution B of FIG. 4A/B or FIG. 5C.
When second page data is written, cells originally in the erased state E are programmed to state A, and those originally in state B′ are programmed to state C. This code scheme has the effect of reducing the potential differences between charge levels of adjacent cells programmed at different times and, therefore, also the field-effect coupling between adjacent floating gates and hence the Yupin effect.
While the code scheme described above in reference to FIGS. 5A and 5C may be advantageous since it reduces the field-effect coupling within adjacent floating gates, user data may be programmed to the wrong states using such code scheme when there is insufficient user data to fill a page as explained below.
Some non-volatile memory arrays may have 2048 bytes per page. This means that 2048 bytes are read or programmed as a single unit in a read or write operation. System programming of non-volatile memory systems may still treat fewer than 2048 bytes, such as 512 bytes, as a unit. Consequently, each of the first and second (e.g. lower and upper) pages may contain a number of sectors, such as four sectors. In other words, when a host is transferring user data to the memory array, towards the end of the data transfer, there may be insufficient user data to completely program all of the memory cells in the page. Thus, if each page has 2048 bytes, there may only be sufficient data to fill the first page and one, two, or three sectors, but not all four sectors of the second page. This is true where a row of memory cells in the memory array contains interleaved pages (where the even page contains all of the memory cells in the row controlled by the even bit lines and the odd page contains all of the memory cells in the row controlled by the odd bit lines) of the type described above, and where a row of memory cells in the memory array contains a single page. Thus, if each row of 2048 memory cells is divided into two interleaved pages, such as odd and even pages, so that each page contains 1024 bytes, there may only be adequate or sufficient data to fill the even or odd first page and one but not both of the sectors of the even or odd second page. With the type of code scheme illustrated in FIGS. 4A and 4B, this does not create a problem. However, where a different code scheme is used, such as those shown in FIGS. 5A, 5B and 5C described above, this can become a problem as illustrated below.
This issue is illustrated in the example of FIGS. 6A and 6B. In this example, a row in a memory array contains 16,384 memory cells for storing 2048 bytes of data, which constitutes one page. The computer host system transferring data to or from the memory array does so in four blocks each with 512 bytes. Thus, as illustrated in FIG. 6A, the row of memory cells in the array is divided or grouped into four sectors or groups 112, 114, 116 and 118, each of the cells in each group storing a first (lower) and second (upper) page of data. As used hereinafter, the terms “sector” and “group” are used interchangeably. As indicated in FIG. 6A, there is enough host data to fill the first or lower page, so that the four first or lower page sectors are marked “L” to so indicate. Towards the end of the block of user or host data to be programmed, there may only be enough data for programming the lower or first page of the four sectors and only the first sector of the second or upper page of the cells in group 112, which is marked “U” in FIG. 6A to so indicate, so that there is no data left for programming the upper or second pages of cells in sectors or groups 114, 116 and 118 of FIG. 6A, where these are left blank without the marker “U” to so indicate.
Before the user data is used for programming the memory cells in the different groups, the data is first loaded into corresponding data buffers or latches (see FIGS. 7, 8A and 8B). The user data stored in the data latches are then used for programming the memory cells. FIG. 6B is a functional block diagram illustrating the function of the data latches for storing the first and second pages of four blocks of data 112′, 114′, 116′ and 118′ for programming the four corresponding sectors or groups 112, 114, 116 and 118 of memory cells of FIG. 6A. After block erase and before the user or host data is loaded into the data latches for programming the cells in the four groups, all of the data latches are loaded with “1” initially. In the example above, the user data is sufficient only for programming the lower or first page of the four groups of memory cells and the upper page of cells in group 112 only. Therefore, as illustrated in FIG. 6B, the upper or second page of the data latches for storing data blocks 114′, 116′ and 118′ have all been loaded with and continue to contain “1.” As shown in FIG. 6B, for example, depending on the user data loaded into the lower or first page in the three blocks of data 114′, 116′ and 118′, some of the memory cells (e.g. those programmed with data 130′, 132′, 134′, 136′ and 138′) would not be programmed where the data in the data latches in the three sectors has the value “11.” However, where the data in the three blocks 114′, 116′ and 118′ has the value “10,” (e.g. data 122′, 124′, 126′ and 128′) the corresponding memory cells in sectors or groups 114, 116 and 118 would be programmed until the threshold voltages or storage levels correspond to the state “10” according to a code scheme.
Then when another block of user or host data is subsequently loaded to displace the default value “1” in the data latches storing blocks 114′, 116′ and 118′, such data typically would not all be of the value “1,” but would contain some values that are “0.” Thus, for some of the memory cells (e.g. cells with data 122′-128′) in groups 114, 116 and 118 that have been programmed to the state “10,” such cells may need to be programmed to the state “00” instead, if the subsequent block of user or host data loads a “0” instead of a “1” as the second or upper page data into the corresponding data latches for such memory cells. From FIG. 5C, it is observed that the state “10” storage level is the highest level C. Since existing programming techniques do not permit the threshold voltage of storage level of individual memory cells to be reduced apart from the block erase operation, it would not be feasible to reprogram such memory cells from the states “10” to the state “00” if the code scheme of FIGS. 5A-5C is used, which results in the cells being programmed to the wrong state. This is referred to herein as the partial page program problem when using the code scheme in FIGS. 5A-5C.